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QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
FEATURES:
- - - - - - - - JEDEC compatible LVTTL level inputs and outputs 10 output, low skew clock signal buffer Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5805T 25 on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew: * 0.7ns output skew * 0.7ns pulse skew * 1ns part-to-part skew Std., A, and B speed grades (B speed in QSOP package only) Available in QSOP and SOIC packages
QS532805/A/B
DESCRIPTION
The QS532805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of 5 non-inverting outputs. The QS532805 incorporates 25 series termination resistors. This clock buffer product is designed for use in high performance workstations, embedded and personal computing systems using 3V to 3.6V supply voltages. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. The QS532805 can accept 5V input and control signals. The QS532805 is characterized for operation at -40C to +85C.
- -
FUNCTIONAL BLOCK DIAGRAM
OEA 5 INA OA5 OA1
MON 5 INB OB5 OB1
OEB
NOTE: QS532805 has a 25 series termination resistor on each clock output, including monitor.
INDUSTRIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
JULY 2000
DSC-5785/-
QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
VCCA OA1 OA2 OA3 GNDA OA4 OA5 GNDQ OEA IN A 1 2 3 4 5 6 7 8 9 10 20 19 18 17 SO 20-2 16 SO 20-8 15 14 13 12 11 VCCB O B1 O B2 O B3 G NDB O B4 O B5 MON O EB IN B
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) VAC IOUT TSTG TJ Description Supply Voltage to Ground DC Output Voltage VOUT DC Input Voltage VIN AC Input Voltage (pulse width 20ns) DC Output Current VIN < 0 DC Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
(1) Unit V V V V mA mA C C
Max. - 0.5 to +7 - 0.5 to Vcc+0.5 - 0.5 to +7 -3 -20 120 - 65 to +150 150
QSOP/ SOIC TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc.
CAPACITANCE
(TA = +25OC, f = 1.0MHz, VIN = 0V, VOUT = 0V)
Pins CIN COUT Typ. 4 8 Max. (1) 6 10 Unit pF pF
NOTE: 1. This parameter is guaranteed but not production tested.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA Description Power Supply Voltage Input Voltage Voltage Applied to Outputs Ambient Operating Temperature Min. 3 0 0 - 40 Max 3.6 5.5 VCC 85 Unit V V V C
PIN DESCRIPTION
Pin Names OEA, OEB INA, INB OAn, OBn MON I/O I I O O Description Output Enable Clock Inputs Clock Outputs Monitor Outputs (does not 3-state)
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QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 3.3V 0.3V
Symbol VIH VIL VIC VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Clamp Diode Voltage (3) Output HIGH Voltage Output LOW Voltage Test Conditions Guaranteed Logic HIGH for Inputs Guaranteed Logic LOW for Inputs Vcc = Min., IIN = -18mA Vcc = Min., IOH = -100A Vcc = Min., IOH = -8mA Vcc = Min., IOL = 100A Vcc = Min., IOL = 6mA Vcc = Min., IOL = 8mA IIN IOZ IOFF IODH IODL IOS ROUT Input Leakage Current Output Leakage Current Input Power Off Leakage Output HIGH Current (2) Output LOW Current (2) Short Circuit Current Output Resistance
(2,3) (4)
Min. 2 -0.5 -- Vcc - 0.2 2.4 -- -- -- -- -- -- -30 30
Typ.(1) -- -- -0.7 -- -- -- -- -- -- -- -- -100 100 -- 28
Max. 5.5 0.8 -1.2 -- -- 0.2 0.4 0.5 1 1 1 -200 200 -- --
Unit V V V V V V V V A A A mA mA mA
Vcc = Max., VIN = Vcc or GND Vcc = Max., VOUT = Vcc or GND Vcc = 0V, VIN = Vcc or GND Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V Vcc = Max., VOUT = GND Vcc = Min
- 60
--
NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICC ICCD IC Parameter Quiescent Power Supply Current Supply Current per Input HIGH Dynamic Power Supply Current per Output (2) Total Power Supply Current Examples (2,4) Test Conditions (1) VCC = Max., VIN = GND or Vcc VCC = Max., VIN = Vcc - 0.6V, f = 0MHz VCC = Max., OEA = OEB = GND Outputs Toggling at 50% duty cycle VCC = Max., VIN = GND or Vcc OEA = OEB = GND 50% duty cycle, fI = 10MHz VIN = GND or 3V five outputs toggling VCC = Max., VIN = GND or Vcc OEA = OEB = GND 50% duty cycle, fI = 2.5MHz VIN = GND or 3V All outputs toggling Typ. (3) 0.01 0.1 65 3.3 3.3 1.8 1.8 Max. 100 30 100 5.2 5.2 2.9 2.9 Unit A A A/MHz mA mA mA mA
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Guaranteed by design but not tested. CL = 0pF. 3. Typical values are for reference only. Conditions are VCC = 3.3V, TA = 25C. 4. IC = ICC + (ICC)(DH)(NI) + ICCD (fO)(NO) where: DH = Input Duty Cycle NI = Number of TTL HIGH inputs at DH fO = Output Frequency NO = Number of outputs at fO
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QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SKEW CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 3.3V 0.3V CLOAD = 50pF (no resistor)
QS532805 Symbol tSK(01) tSK(02) tSK(P) tSK(T) Parameter (1) Skew between all outputs, same transition, same bank Skew between two outputs, same transition, different banks Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) Part-to-part skew (2) Min. -- -- -- -- Max. 0.7 0.9 1 1.5 QS532805A Min. -- -- -- -- Max. 0.7 0.9 0.7 1 QS532805B (3) Min. -- -- -- -- Max. 0.7 0.9 0.5 1 Unit
ns ns ns ns
NOTES: 1. This parameter is guaranteed but not production tested. Skew parameters apply to propagation delays only. 2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading package, and speed grade. 3. The B speed grade is only available in the QSOP package.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 3.3V 0.3V CLOAD = 50pF (no resistor)
QS532805 Symbol tPLH tPHL tR tF tPZL tPZH tPLZ tPZH Parameter (1,2) Propagation Delay Output Rise Time, 0.8V to 2V (3) Output Fall Time, 2V to 0.8V (3) Min. 1.5 -- -- 1.5 1.5 Max. 6.5 2 2 8 7 QS532805A Min. 1.5 -- -- 1.5 1.5 Max. 5.8 2 2 8 7 QS532805B (4) Min. 1.5 -- -- 1.5 1.5 Max. 5.2 2 2 6.5 6 Unit
ns ns ns ns ns
Output Enable Time Output Disable Time
NOTES: 1. Minimums guaranteed but not production tested. 2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delays do not imply limit skew. 3. This parameter is guaranteed but not production tested. 4. The B speed grade is only available in the QSOP package.
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QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
Parameter Tested
Switch Position
tPLZ, tPZL All Others VCC VIN Pulse Generator 50 DUT 50pF 500 VOUT 500
Closed Open
6.0 V
Pulse generator for all pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns
3V INPUT tPLH tPHL VOH 2.0V 1.5V 0.8V VOL tR tF tPLH OUPUT tPHL VOH 1.5V VOL tSK(p) = tPHL - tPLH 1.5V 0V INPUT 3V 1.5V 0V
OUPUT
PROPAGATION DELAY
PULSE SKEW -- tSK(P)
3V 3V INPUT tPLHA VOH tPHLA VOH OUPUT A 1.5V VOL tSK(02) OUPUT B tSK(02) VOH 1.5V VOL tPLHB tPHLB 1.5V 0V
INPUT tPLH1 tPHL1
1.5V 0V
OUPUT 1
1.5V VOL tSK(01) tSK(01) VOH 1.5V VOL tPLH2 tPHL2 tSK(01) = tPLH2 - tPLH1 or tPHL2 - tPHL1
OUPUT 2
tSK(02) = tPLHB - tPLHA or tPHLB - tPHLA
OUTPUT SKEW (SAME BANK) -- tSK(O1)
OUPUT SKEW (DIFFERENT BANKS) -- tSK(O2)
ENABLE CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SWITCH CLOSED tPZH OUTPUT NORMALLY HIG H SWITCH OPEN 1.5V
DISABLE 3V 1.5V 0V tPLZ 3V 1.5V 0.3V VOL tPHZ 0.3V VOH PART 2 O UTPUT tSK(t) tSK(t) PART 1 O UTPUT INPUT tPLH1 tPHL1 VOH 1.5V VOL VOH 1.5V VOL 0V tPLH2 tPHL2 3V 1.5V 0V
tSK(t) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ENABLE AND DISABLE TIMES 5
PART-TO-PART SKEW -- tSK(T)
QS532805/A/B GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXX Device Type XX Package
Q SO
Quarter Size Small Outline Pacakge (SO20-8) Small Outline IC (SO20-2)
532805 Guaranteed Low Skew 3.3V CMOS Clock Driver/Buffer 532805A (532805B) (QSOP package only)
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